1. Field of the Invention
The present invention relates to an analog/digital converter circuit (hereinafter abbreviated as an A/D converter circuit) for converting an analog signal to a digital signal, and more particularly the present invention relates to a serial/parallel type A/D converter circuit for converting an analog signal to a digital signal with two stages that form an upper data part and a lower data part.
2. Description of the Related Art
Various types of analog-to-digital conversion systems have been proposed, in one such system known as a parallel-type (flash-type) A/D converter the circuit quantizes the amplitude of the analog signal and converts the quantized signal to a digital code.
In such a parallel-type A/D converter circuit, high speed operation is possible, however when the number of the conversion bits is n, at least (2.sup.n -1) comparators are necessary for implementation of the circuit. A total of 255 comparators are necessary to obtain an 8-bit conversion code, and it is necessary to form several tens of thousands active elements by integration into a circuit in order to obtain a digital code having higher resolution.
For this reason, a parallel-type A/D converter circuit has the advantage that high speed processing is possible, but it is undesirable due to increases in which is required power consumption and the large surface area for the chip.
Therefore, a so-called serial/parallel type A/D converter circuit has been proposed in which, for conversion of the analog signal to n bits of resolution. In this circuit first the analog signal is digitized by rough quantization, so that an "a" bit conversion code including the most significant bit (MSB) is obtained, and in order to reduce the error of this upper data conversion code, that is, the quantization noise, the upper data quantization range is finely divided and digitized, so that the lower data [b (n-a)] bit conversion code including the lower significant bit (LSB) is obtained.
FIG. 1 is a structural view showing an outline of one such serial/parallel type A/D converter circuit which illustrates the circuit configuration for converting an analog signal to a 4-bit digital code.
In FIG. 1, R.sub.1 to R.sub.16 denote reference resistance elements serially connected between terminals of reference voltages V.sub.RT to V.sub.RB (0 to -2 V); C.sub.u1 to C.sub.u3 denote upper data comparators which have one input terminal connected to an input line of an input analog signal V.sub.IN to be converted and the other input terminal connected to the input line of the reference voltages (V.sub.4, V.sub.8, V.sub.12) of the rough quantization level divided by reference resistance elements R.sub.1 to R.sub.16 ; B.sub.u1 to B.sub.u3 denote buffers for obtaining the complementary outputs of the outputs of upper data comparators C.sub.u1 to C.sub.u3 ; A.sub.u1 to A.sub.u4 denote AND gates; S.sub.a1 to S.sub.a12 denote switching blocks arranged in the form of a matrix comprising four rows and three columns; C.sub.d1 to C.sub.d3 denote lower data comparators with one input terminal connected to the input line of the analog signal V.sub.IN and the other side input terminal connected to the output terminals of the switching blocks S.sub.a1 to S.sub.a12 ; E.sub.u1 denotes an upper data encoder which encodes the result of differentiation of binary signals output from the upper data comparators C.sub.u1 to C.sub.u3 and converts the same to for example a 2-bit binary code (or complementary code of 2); and E.sub.d1 denotes a lower data encoder which converts the result of differentiation of the binary signals output from the lower data comparators C.sub.d1 to C.sub.d3 to a 2-bit binary code; respectively.
The switching blocks S.sub.a1 to S.sub.a12 are controlled to turn on or off in accordance with the data "1" and "0" of the output level of the AND gates A.sub.u1 to A.sub.u4.
For example, when a signal of the "1" level is output from the AND gate A.sub.u1, control is performed so that the switching blocks S.sub.a1 to S.sub.a3 become an ON state; when the signal of the "1" level is output from the AND gate A.sub.u2, control is performed so that the switching blocks S.sub.a4 to S.sub.a6 become an ON state; when the signal of the "1" level is output from the AND gate A.sub.u3, control is performed so that the switching blocks S.sub.a7 to S.sub.a9 become an ON state; and when the signal of the "1" level is output from the AND gate A.sub.u4, control is performed so that the switching blocks S.sub.a10 to S.sub.a12 become an ON state;
In the serial/parallel type A/D converter circuit having such a structure, as shown in for example FIG. 2, the input analog signal V.sub.IN is sampled at the using point of the sampling pulse P.sub.S, and the sampling voltage V.sub.S thereof is supplied to the upper data encoder E.sub.u1 and the lower data encoder E.sub.d1.
At the upper data encoder E.sub.u1, when the sampling voltage V.sub.S is supplied, the binary signal outputs of the upper data comparators C.sub.u1 to C.sub.u3 are converted to the code signals D.sub.0 and D.sub.1 of the upper significant 2 bits at the point of time T.sub.H of trailing edge (point of time lagged by .tau..sub.A) of the clock signal CLK and output.
At the lower data encoder E.sub.d1, when the sampling voltage V.sub.S is supplied, the binary signal outputs of the lower data comparators C.sub.d1 to C.sub.d3 are converted to the code signals D.sub.2 and D.sub.3 of the lower significant 2 bits at the point of time T.sub.L of trailing (point of time lagged by .tau..sub.B) of the clock signal CLK,
Explaining this more concretely, reference voltages V.sub.4, V.sub.8, and V.sub.12 of the rough quantization level, divided by the reference resistance elements R.sub.1 to R.sub.16 and the input analog signal V.sub.IN are compared by the upper data comparators C.sub.u1 to C.sub.u3.
As a result of this comparison, for example, when V.sub.4 &lt;V.sub.IN &lt;V.sub.8, the output of the upper data comparator C.sub.u3 becomes the high level at a high potential ("1"), and the outputs of the upper data comparators C.sub.u2 and C.sub.u3 become the low level at a low potential ("0").
Thus, at the output of the AND gates A.sub.u1 to A.sub.u4, only the output of the AND gate A.sub.u2 becomes "1", and the outputs of the other AND gates A.sub.u1, A.sub.u3, and A.sub.u4 become "0".
As a result, the code [01] is output as the upper significant 2 bits of the conversion code from the upper data encoder E.sub.u1.
Next, in a state where the upper significant 2 bits of the conversion code are latched, the signal of the "1" level output from the AND gate A.sub.u2 is input to the switching blocks S.sub.a4 to S.sub.a6. By this, the switching blocks S.sub.a4 to S.sub.a6 become an ON state.
Along with the switching blocks S.sub.a4 to S.sub.a6 becoming the ON state, the sampled analog signal V.sub.IN existing at the level represented as V.sub.4 &lt;V.sub.IN &lt;V.sub.8 is further divided by the resistance elements R.sub.4 to R.sub.6, and regulated reference voltages V.sub.5, V.sub.6, and V.sub.7 are input via the switching blocks S.sub.a4, S.sub.a5, and S.sub.a6 to the other input terminals of the lower data comparators C.sub.d3, C.sub.d2, and C.sub.d1, respectively.
In the lower data comparators C.sub.d3, C.sub.d2, and C.sub.d1, the input reference voltages V.sub.5, V.sub.6, and V.sub.7 are compared with the analog signal V.sub.IN which is input to the one side input terminals of the same and the result of comparison is output to the lower data encoder E.sub.d1.
As a result of this comparison, when for example V.sub.6 &lt;V.sub.IN &lt;V.sub.7, the lower significant 2 bits of the conversion code [10] are output from the lower data encoder E.sub.d1.
As a result of the above, a 4-bit conversion code [0110] of the analog signal V.sub.IN will be output from the upper data and lower data encoders E.sub.u1 and E.sub.u2.
This serial/parallel type A/D converter circuit outputs the conversion code while dividing the same to upper significant and lower significant 2 bits and therefore can reduce the number of comparators required when performing the A/D conversion of 4 bits to 6.
Also, when for example A/D conversion of 8 bits is to be carried out, as mentioned above, in the parallel type A/D converter circuit, 255 comparators are necessary, but this serial/parallel type A/D converter circuit has an advantage in that only (2.sup.4 -1).times.2=30 comparators are sufficient to provide four upper significant bits and lower significant bits, respectively.
However, since the code conversion is carried out by two stages, during this time, it is necessary to provide a sample and hold circuit so that the input signal voltage is not changed, but is held at a fixed value, consequently leading to inducing complication of the circuit control etc.
In the above-mentioned A/D converter circuit, when increased resolution thereof is desired, a large number of taps from a voltage-division resistance element group becomes necessary, and finer processing of the semiconductor material becomes necessary. The reference voltage value of adjoining comparators becomes smaller if miniaturization is further increased, whereby a so-called offset voltage of the comparator becomes equivalent to the difference, thereby producing problems such as the loss of the comparator characteristics.
Therefore, as a means solving this problem and improving the resolution, a comparator circuit adopting a so-called interpolation construction has been proposed.
FIG. 3 is a schematic circuit diagram showing a conventional comparator circuit adopting this interpolation construction. In FIG. 3, comparators 24 and 25 denote complementary output type comparators; v.sub.in denotes an input analog signal; and v.sub.r1, v.sub.r2 (v.sub.r1 &lt;v.sub.r2) denote reference voltages; respectively.
In this comparator circuit, an imaginary voltage at an intermediate point between two reference voltages v.sub.r1 and v.sub.r2 is obtained from the positive output of the comparator 24 and the negative output of the comparator 25, and the result of comparison of this imaginary voltage with the input analog signal v.sub.in is successively obtained.
This structure has an advantage in that the error resulting from of, for example, the processing precision can be easily absorbed in comparison with a case where a large number of independent taps are adopted as mentioned above. This design however, can merely perform an equal weight between two reference voltages v.sub.r1 and v.sub.r2, and only can obtain an excessive result of comparison with the voltage at an intermediate point between two reference voltages. This design cannot freely obtain an imaginary voltage or a plurality of imaginary voltages.
Accordingly, there are problems in that the resolution of the above-mentioned conventional A/D converter circuit can be raised to only twice its level and improvement exceeding this is difficult, and furthermore, the application range is restricted.
A detailed description will be further made particularly of another design in the related art, which is a modification of the lower data encoder.
FIGS. 4A and 4B illustrate a circuit diagram showing an example of the structure of a conventional A/D converter circuit and shows a circuit structure for converting an analog signal V.sub.IN to a 4-bit digital code.
In FIG. 4A, reference numeral 30 denotes a matrix circuit; 61 to 60 denote upper data comparators; 63 denotes an upper data encoder; 31 to 37 denote lower data comparators; 40 denotes a lower data encoder; 64 an inverted gate; 65 an inhibit gate; 66 a selection gate; and 67 an inverter; respectively.
The matrix circuit 30 is comprised of 28 switching blocks S.sub.b11 to S.sub.b17, S.sub.21 to S.sub.b27, S.sub.b31 to S.sub.b37, and S.sub.b41 to S.sub.b47 arranged in the form of a matrix comprising 4 rows and 7 columns.
The switching blocks S.sub.b11 to S.sub.b17, S.sub.b21 to S.sub.b27, S.sub.b31 to S.sub.b37 and S.sub.b41 to S.sub.b47 are comprised of differential-type amplifiers comprising npn-type transistors Q.sub.1, Q.sub.2, and Q.sub.3.
Except for parts, reference voltages obtained by dividing the reference voltages V.sub.RT -V.sub.RB by the reference resistance elements R.sub.31 to R.sub.46 are supplied to the base of one transistor Q.sub.1 constituting a so-called differential pair, and the analog signal V.sub.IN to be converted to the digital code is supplied to the base of the other transistor Q.sub.2, respectively.
Also, emitters of the transistors Q.sub.1 and Q.sub.2 are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q.sub.3 which is switched by the control signal mentioned later.
Also, a power source voltage V.sub.DD is supplied to the collectors of the transistors Q.sub.1 and Q.sub.2 via the resistor r. The output terminals thereof are connected to the inputs to the comparators C.sub.D1 to C.sub.D7 of seven lower data comparators 31 to 37, respectively. Joint use is made of the first stage amplifiers of the lower data comparators 31 to 47.
In the figure, switching blocks S.sub.b11, S.sub.b12, S.sub.b16, S.sub.b17, S.sub.b21, S.sub.b22, S.sub.b26, S.sub.b27, S.sub.b31, S.sub.b32, S.sub.b36, S.sub.b37, S.sub.b41, S.sub.b42, S.sub.b46, and S.sub.b47 further output 2LSB redundant bits with respect to 2-bit lower data conversion code. Particularly, among them, S.sub.b11, S.sub.b12, S.sub.b41, and S.sub.b42 are given fixed input signals so that a constant binary signal "H" or "L" is output when activation is made by the control signal.
Also, particularly, a system is devised so that the collectors of the transistors Q.sub.1 and Q.sub.2 at the second row and fourth row of the switching block are connected to the line in an opposite direction to the collector outputs of the transistors Q.sub.1 and Q.sub.2 at the first row and the third row of the switching block, whereby the lines of the serially connected reference resistance elements R.sub.1 to R.sub.16 applied with the reference potentials (voltages) V.sub.RT -V.sub.RB can be formed by folding-back.
Each of the three upper data comparators 61, 62, and 63 is provided with the comparators C.sub.U5 to C.sub.U7, complementary-type output amplifiers CA, and AND gates A.sub.u5 to A.sub.u8, respectively.
An analog signal V.sub.IN is supplied to one side inputs of the respective comparators C.sub.U of the upper data comparators 61 to 63, and reference voltages V.sub.1, V.sub.2, and V.sub.3 obtained by dividing the reference potentials V.sub.RT to V.sub.RB by the rough quantization are supplied to the other side inputs.
The outputs of the respective comparators C.sub.U of the upper data comparators 61 to 63 become the level of "H" or "L" corresponding to the level of the sampled analog signal and are set so that only one of the respective AND gates A.sub.U outputs the "1" level.
The output signals of the respective AND gates A.sub.U are wired-connected and converted to a binary code via the upper data encoder 60. In the selection gate 66 mentioned later, correction is applied to the upper significant two bits of the codes D.sub.1 and D.sub.2.
Also the lower data comparators 31 to 37 are formed in the same way as the upper data comparators 61 to 63. Particularly, the lower data comparators 33, 34, and 35 further finely digitize the inside of the quantization level selected by the upper data comparator and output the lower significant 2 bits of the codes D.sub.3 and D.sub.4 via the lower data encoder 40.
Further, this A/D converter circuit is designed so that comparators 31, 32, 36, and 37 produce the redundant code of 2LSB which are provided on the left and right of this lower data comparator, and the code conversion operation is carried out also for the analog signal V.sub.IN out of the conversion range of the lower data comparator, specified by the upper data comparators 61 to 63.
In such a structure, for example when the sampling voltage V.sub.S of the sampled analog signal is represented as V.sub.RB &lt;V.sub.S &lt;V.sub.3, the outputs of comparators C.sub.U of the upper data comparators 61, 62, and 63 become all "L", so that the binary signal output, is "0" which output from the AND gates A.sub.u5 to A.sub.u7, and "1" is output from A.sub.u8, respectively.
As a result, a binary signal [0001] is input to the upper data encoder 63, and by a so-called wired-OR circuit, [00] is output to the first two lines [LN.sub.5 ]; [00] is output also to the next two lines [LN.sub.6 ], and [01] is output to the next two lines [LN.sub.7 ].
When the sampling voltage V.sub.S is represented as V.sub.3 &lt;V.sub.S &lt;V.sub.2, similarly the binary signal of "0" is output from the upper data side AND gates A.sub.U5, A.sub.U6, and A.sub.U8, and the binary signal "1" is output from the gate A.sub.U7, respectively.
As a result, a binary signal such as [0010] is input to the upper data encoder 63, so that [00] is output from the line [LN.sub.5 ]; [01] is output from the line [LN.sub.6 ]; and [10] is output from the line [LN.sub.7 ].
Below, the relationship between the input and output of the upper data encoder 60 including the case where V.sub.2 &lt;V.sub.S &lt;V.sub.1 and V.sub.1 &lt;V.sub.S &lt;V.sub.RT is as shown in FIG. 5.
In parallel to this, the transistors Q.sub.3 of the respective switching blocks connected to the control lines (x.sub.5, x.sub.6, x.sub.7, and x.sub.8) at which the binary output signal has become "1", among the respective AND gates A.sub.U(5, 6, 7, 8), is set to ON, and further the fine digitization of the quantization level is executed.
For example, when only the output of the AND gate A.sub.U7 becomes a "1" level, the transistors Q.sub.3 of the switching blocks S.sub.b31 to S.sub.b37 turn ON, so that the reference voltage divided by the reference resistance elements R.sub.37 to R.sub.43 and the sampling voltage V.sub.S are differentially amplified at the switching blocks S.sub.b31 to S.sub.b37 and compared by the lower data comparators 31 to 37.
Similarly, the switching blocks S.sub.b21 to S.sub.b27 are activated when the output of the AND gate A.sub.U6 is at the "1" level, a differential amplification operation is carried out, and the comparison by the lower data comparators 31 to 37 is carried out.
In this way, in the lower data code, the sampled voltage V.sub.S and the reference voltage divided by the reference resistance element of that row are compared in units of rows of the switching block, the binary signals are output from the AND gates A.sub.D1 to A.sub.D7 and A.sub.D8 of the lower data comparators 31 to 37 as shown in FIG. 6, and these binary signals are encoded at the lower data encoder 40, whereby the lower significant 2 bits of the conversion codes D.sub.3 and D.sub.4 are output from the lower data code line [LN.sub.1 ].
Moreover, the output levels of the selection lines LN.sub.2, LN.sub.3, and LN.sub.4 are changed as shown in FIG. 6.
Then, as indicated below by a, b, and c, when a signal of the "1" level is output to either of these selection lines LN.sub.2, LN.sub.3, and LN.sub.4, the upper significant 2 bits of the conversion codes D.sub.1 and D.sub.2 from the lines LN.sub.5, LN.sub.6, and LN.sub.7 in the upper data encoder 30 are selectively output via the OR gates OR.sub.1 and OR.sub.2.
(a) When the conversion code with which "1" is produced in the selection line LN.sub.3 (0 line), that is, the lower significant 2 bits of the conversion codes D.sub.3 and D.sub.4 become [00], [10], and [11] corresponding to the upper data conversion codes, the outputs of the AND gates A.sub.1 and A.sub.2 constituting the inhibit gate 65 become "0", and therefore the outputs of the AND gates A.sub.1, A.sub.3, A.sub.4, and A.sub.6 existing inside the selection gate 66 become "0".
As a result, the upper data D.sub.1 and D.sub.2 codes of the line [LN.sub.6 ] output from the upper data encoder 63 are output as they are via the AND gates A.sub.2 and A.sub.5 of the selection gate 66 and the OR gates OR.sub.1 and OR.sub.2.
This case of (a) indicates a case where the level of the analog signal when performing the conversion of the upper significant 2 bits is not changed from the analog signal when performing the conversion of the lower significant 2 bits, and the correction is not carried out.
(b) Where the selection line LN.sub.2 is "1" and the AND gate A.sub.U5 or A.sub.U7 is "1", and where the selection line LN.sub.4 is "1" and the AND gate A.sub.U8 or A.sub.U6 is "1", the AND gate A.sub.1 constituting the inhibit gate 65 is opened. As a result, the upper significant 2 bits of the codes D.sub.1 and D.sub.2 of the line LN.sub.5 input to the AND gates A.sub.1 and A.sub.4 are output via the OR gates OR.sub.1 and OR.sub.2.
This case of (b) performs the correction where the level of the analog signal when digitizing the upper significant 2 bits D.sub.1 and D.sub.2 is higher than the analog signal when digitizing the lower significant 2 bits D.sub.3 and D.sub.4.
For example, as shown in FIG. 7, when the truth value of the sampling value V.sub.S of the analog signal is V.sub.A, and when the conversion code of the upper significant 2 bits is erroneously output at [10] and output at a correct lower significant 2 bits of the conversion code [11] from the lower data comparator, "1" is subtracted from the upper significant 2 bits of the conversion code [10], and corrected to [01], thereby obtaining a correct code output [0111].
Namely, this case means that the control line erroneously selects the line of the switching block, but since the lower data comparator 46 on the right side detecting the redundant bit outputs [00], the upper significant 2 bits of the conversion code will be corrected.
(c) Where the selection line LN.sub.4 is "1" and the AND gate A.sub.U5 or A.sub.U7 is "1", and where the selection line LN.sub.2 is "1" and the AND gate A.sub.U8 or A.sub.U6 is "1", the output of the AND gate A.sub.2 constituting the inhibit gate 65 becomes "1", and the AND gates A.sub.3 and A.sub.6 of the selection gate 66 are opened.
As a result, the upper significant 2 bits of the codes D.sub.1 and D.sub.2 of the line LN.sub.7 input to these AND gates A.sub.3 and A.sub.6 are output via the OR gates OR.sub.1 and OR.sub.2, and "+1" is added to the upper significant 2 bits of the codes.
Namely, in this case of (c), where the sampling level of the analog signal when digitizing the upper significant 2 bits of D.sub.1 and D.sub.2 is lower than the quantization level range at that time, a correction is applied.
For example, when the truth value of the analog signal V.sub.IN exists at the point of V.sub.B, when the upper significant 2 bits become [00], if the numerical value of the lower significant 2 bits is output as [00], "+1" is added to the upper significant 2 bits [00], to obtain [01], and the [0100] corresponding to the sampling voltage .sub.VB of the correct analog signal is output.
This A/D converter circuit adds a comparator for detecting the redundant bit to the lower data comparator as described above, outputs, when the lower data conversion code out of the range of the upper data conversion code (region indicated by a hatching in FIG. 7), a signal of the "1" level to the selection line LN.sub.2 or LN.sub.4, and performs the correction of the upper data conversion code, and therefore has an advantage that a correct conversion code detected at the point of time of lower data can be obtained by high speed sampling even when the settling characteristic of the sampling circuit is poor.
As mentioned above, in the conventional circuit, for correcting the upper data code, a correction is carried out based on the concept of adding "1" and subtracting "1".
For this reason, it is constituted so that, in the upper data, normal data and lower redundant data (data obtained by subtracting "1" from the normal data) and the upper redundant data (data obtained by adding "1" to the normal data) are settled into respective groups, and one is selected from among the three groups by a selection signal from the lower data encoder.
Nevertheless, there alternately exists a column in which the right part of the resistance column becomes the lower redundancy and a column in which it becomes the upper redundancy. Accordingly, there is a case where the lower data encoder connected to the right part of the resistance column selects the lower redundant data and a case where it selects the upper redundant data.
Accordingly, the data to be selected differs for each column, and therefore the inverted gate 64 and inhibit gate 65 were necessary for controlling this.
However, the selection signal from the lower data encoder 50 (LN.sub.2, LN.sub.3, and LN.sub.4 in the diagram) passes through the inverted gate 64 and the inhibit gate 65, and then is transferred to the selection gate 66, and therefore the selection signal is input to the selection gate 66 with a time lag relative to the upper data output from the upper data encoder 63.
For this reason, a delay due to the existence of the inverted gate 64 and the inhibit gate 65 occurs in the output processing of the conversion code, consequently leading to a problem that the conversion time of the A/D converter circuit is increased.
Moreover, there also exists a problem in that increases of the chip area and power consumption are induced since an excessive quantity of inverted gates and inhibit gates become necessary.
Further, there also exists another problem in that, in addition to the necessity of an excessive quantity of inverted gates and inhibit gates, three selection signals become necessary, and three sets of upper data codes to be selected become necessary too, and also the number of input gates in the selection gate is increased, and therefore resulting in increases of the chip area and power consumption.
Further, so as to obtain the upper significant "a" bits, (2.sup.a -1) upper data comparators are necessary, and 2.sup.a rows become necessary too also for a row of the switching block. This is one of the causes of an increase of the chip area and the power consumption.